Non-volatile memory devices are well known in the art. For example, a split-gate memory cell is disclosed in U.S. Pat. No. 5,029,130. This memory cell has a floating gate and a control gate disposed over and controlling the conductivity of a channel region of the substrate extending between source and drain regions. Various combinations of voltages are applied to the control gate, source and drain to program the memory cell (by injecting electrons onto the floating gate), to erase the memory cell (by removing electrons from the floating gate), and to read the memory cell (by measuring or detecting the conductivity of the channel region to determine the programming state of the floating gate).
The configuration and number of gates in non-volatile memory cells can vary. For example, U.S. Pat. No. 7,315,056 discloses a memory cell that additionally includes a program/erase gate over the source region. U.S. Pat. No. 7,868,375 discloses a memory cell that additionally includes an erase gate over the source region and a coupling gate over the floating gate.
FIG. 1 illustrates a split gate memory cell 10 with spaced apart source and drain regions 14/16 formed in a silicon semiconductor substrate 12. A channel region 18 of the substrate is defined between the source/drain regions 14/16. A floating gate 20 is disposed over and insulated from a first portion of the channel region 18 (and partially over and insulated from the source region 14). A control gate (also referred to as a word line gate or select gate) 22 has a lower portion disposed over and insulated from a second portion of the channel region 18, and an upper portion that extends up and over the floating gate 20 (i.e., the control gate 22 wraps around an upper edge of the floating gate 20).
Memory cell 10 can be erased by placing a high positive voltage on the control gate 22, and a reference potential on the source and drain regions 14/16. The high voltage drop between the floating gate 20 and control gate 22 will cause electrons on the floating gate 20 to tunnel from the floating gate 20, through the intervening insulation, to the control gate 22 by the well-known Fowler-Nordheim tunneling mechanism (leaving the floating gate 20 more positively charged—the erased state). Memory cell 10 can be programmed by applying a ground potential to drain region 16, a positive voltage on source region 14, and a positive voltage on the control gate 22. Electrons will then flow from the drain region 16 toward the source region 14, with some electrons becoming accelerated and heated whereby they are injected onto the floating gate 20 (leaving the floating gate negatively charged—the programmed state). Memory cell 10 can be read by placing ground potential on the drain region 16, a positive voltage on the source region 14 and a positive voltage on the control gate 22 (turning on the channel region portion under the control gate 22). If the floating gate is more positively charged (erased), the positive voltage on the control gate will at least partially couple to the floating gate to turn on the channel region portion under the floating gate, and electrical current will flow from source region 14 to drain region 16 (i.e. the memory cell 10 is sensed to be in its erased “1” state based on sensed current flow). If the floating gate 20 is negatively charged (programmed), the coupled voltage from the control gate 22 will not overcome the negative charge of the floating gate, and the channel region under the floating gate is weakly turned on or turned off, thereby reducing or preventing any current flow (i.e., the memory cell 10 is sensed to be in its programmed “0” state based on sensed low or no current flow).
FIG. 2 illustrates an alternate split gate memory cell 30 with same elements as memory cell 10, but additionally with a program/erase (PE) gate 32 disposed over and insulated from the source region 14 (i.e. this is a three gate design). Memory cell 30 can be erased by placing a high voltage on the PE gate 32 to induce tunneling of electrons from the floating gate 20 to the PE gate 32. Memory cell 30 can be programmed by placing positive voltages on the control gate 22, PE gate 32 and source region 14, and a current on drain region 16, to inject electrons from the current flowing through the channel region 18 onto floating gate 20. Memory cell 30 can be read by placing positive voltages on the control gate 22 and drain region 16, and sensing current flow.
FIG. 3 illustrates an alternate split gate memory cell 40 with same elements as memory cell 10, but additionally with an erase gate 42 disposed over and insulated from the source region 14, and a coupling gate 44 over and insulated from the floating gate 20. Memory cell 40 can be erased by placing a high voltage on the erase gate 42 (and optionally a negative voltage on the coupling gate 44) to induce tunneling of electrons from the floating gate 20 to the erase gate 42. Memory cell 40 can be programmed by placing positive voltages on the control gate 22, erase gate 42, coupling gate 44 and source region 14, and a current on drain region 16, to inject electrons from the current flowing through the channel region 18 onto floating gate 20. Memory cell 30 can be read by placing positive voltages on the control gate 22 and drain region 16 (and optionally on the erase gate 42 and/or the coupling gate 44), and sensing current flow.
For all the above referenced memory cells, voltages are applied in each of the program, erase and read operations to program the memory cells to a “0” state, erase the memory cells to a “1” state, and to read the memory cells to determine whether they are in the programmed state or the erased state. One drawback to such memory devices is that each memory cell can only store one bit of data (i.e., the cell has only two possible states). There is a need to program more than one bit of data in each memory cell. It is also known to operate the above described memory cells in an analog fashion so that the memory cell can store more than just two binary values (i.e., just one bit of information). For example, the memory cells can be operated below their threshold voltage, meaning that instead of fully programming or fully erasing the memory cells, they can be only partially programmed or partially erased, and operated in an analog fashion below the threshold voltage of the memory cell. It is also possible to program the memory cells to one of multiple program states above the threshold voltage too. However, if discrete programming states are desired, it can be difficult to reliably program and read the memory cells because the read current values for the various states are so close together.